Why UVM RAL model is required in RTL verification?
Let's try to find the answer. Normally any RTL/design works as per its configuration which is normally done by either IOs or register configuration. So the first step of any RTL/Design verification is its register verification, where register accessibility, attributes and functionality is verified. Here Verification engineer needs to make sure that each register field is verified with all possible/valid values. Manual verification of each register field is tedious and time consuming task. Also register attribute verification is almost common approach across various projects. UVM provides efficient and automated way for register attribute verification as well as register access. Below are some features provided by UVM RAL. - Supports different register attributes like RW, RC, RO, WO, W1C, W0C, R1C, etc. - Supports backdoor register access for fast simulation mode - Same RAL model can be used with different Interface protocol using different RAL adapter. - Built-in reg...